In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases, often referred to as multi-phase clocks. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
FIG. 1 is a block diagram of a conventional multiple phase-based clock/timing recovery system 100. As shown in FIG. 1, a ring oscillator 110 comprised of a cascaded chain of delay elements generates a multi-phase clock. The multi-phase clock is comprised of a number of different clock signals CK0-CKN−1 having the same frequency but with different phases. The multi-phase clock is then applied to a corresponding amplifier 120 before being applied to a phase selection multiplexer 130. A clock recovery loop 140 generates a phase selection control that is applied to the phase selection multiplexer 130. The phase selection multiplexer 130 then selects one of the clocks CK0-CKN−1 that is phase-aligned with the incoming data.
The system 100 requires that the multi-phase clocks demonstrate good phase linearity. If a ring oscillator comprised of a cascade of delay cells is used to generate the multi-phase clocks, the phase linearity (i.e., phase step between adjacent phases) is determined by the matching properties of the delay cells. Large devices are generally required to improve the matching, which consume a large area and a significant amount of power. Furthermore, the post-amplifier 120 and phase selector 130 add more phase nonlinearity. In addition, the multi-phase clocks are often generated using a higher frequency clock and then deriving the required phases by dividing down the high frequency clock. The high frequency oscillator will consume a significant amount of power.
A need therefore exists for methods and apparatus that improve the phase linearity in a multi-phase based clock recovery system.